Electronic Design1d
Highlights from the RISC-V Summit 2024
Andes Technology's Yueh-Feng Lee presented LLM Inference on RISC-V Embedded CPUs. This presentation highlights the ...
Semiconductor Engineering6d
RISC-V Conformance
Finding out if a processor implementation matches the specification is important, but conformance testing is currently not ...
Nvidia projected to ship roughly a billion RISC-V cores in its products by year's end
Nvidia has apparently been utilizing the RISC-V architecture for quite some time. As one of the most valued technology ...
tom's Hardware on MSN8d
RISC-V CPU demoed with RX 7900 XTX GPU in Debian Linux — AMD flagship GPU paired with Milk-V Megrez board and SiFive P550 cores
RISC-V firm Milk-V demonstrated that it can get AMD’s RX 7900 XTX graphics card to work on one of its RISC-V boards.
Liliputing1d
Waveshare ESP32-P4-Nano is a tiny RISC-V dev board with Ethernet, WiFi, and Bluetooth
The Waveshare ESP32-P4-Nano is a tiny, inexpensive, low-power development board powered by a dual-core RISC-V processor. Available now from Waveshare or AliExpress for around $19 and up, the little ...
Hackaday10mon
CH32 RISC-V MCUs Get Official Arduino Support
Like many of you, we’ve been keeping a close eye on the CH32 family of RISC-V microcontrollers from WCH Electronics. You can get the CH32V003, featuring 2 kB RAM ...
CNX Software2d
Giveaway Week 2024 – Jupiter RISC-V mini-ITX motherboard
CNX Software's Giveaway Week 2024 has started and the first prize will be the MILK-V Jupiter RISC-V motherboard with an M1 ...
Electronic Products5d
RISC-V processor targets functional safety
Andes Technology unveiled its AndesCore 32-bit, 8-stage D45-SE RISC-V processor with ISO 26262 ASIL-D certification.
Hackaday8mon
Bring Linux To CH32V003 Through, Yes, RISC-V Emulation
Running Linux on this chip is only possible thanks to [chlohr]’s mini-rv32ima project, which, as you might remember, is a RISC-V emulator. Yes, this runs Linux by running a RISC-V emulator on a ...
Design-Reuse5y
Extending RISC-V ISA With a Custom Instruction Set Extension
RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...
Digi Times7d
China pushing domestically developed AI chips and deployment of RISC-V structure, says DIGITIMES Research
DIGITIMES Research observes that China is rapidly advancing in the field of LLMs. Major technology giants such as Baidu, ...
Business Wire1mon
SiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration
SANTA CLARA, Calif.--(BUSINESS WIRE)--Today, SiFive, Inc. the gold standard for RISC-V computing, announced the SiFive Intelligence TM XM Series designed for accelerating high performance AI ...